Register 27: Ethernet PHY Management Register 29 – Interrupt Status (MR29),
address 0x1D
This register contains information about the source of PHY layer interrupts. Reading this register
clears any bits that are set. The PHYINT bit is set in the MACRIS/MACIACK register whenever any
of the bits in this register are set.
Ethernet PHY Management Register 29 – Interrupt Status (MR29)
Base 0x4004.8000
Address 0x1D
Type RO, reset 0x0000
0123456789101112131415
reserved
PRXISPDFISLPACKISLDISRFLTIS
ANCOMPIS
EONISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved15:8
ENERGYON Interrupt
DescriptionValue
An interrupt has been generated due to the ENON bit being set
in the MR17 register.
1
No interrupt.0
This bit is cleared by reading the value.
0ROEONIS7
Auto-Negotiation Complete Interrupt
DescriptionValue
An interrupt has been generated due to the completion of auto
negotiation.
1
No interrupt.0
This bit is cleared by reading the value.
0ROANCOMPIS6
Remote Fault Interrupt
DescriptionValue
An interrupt has been generated due to the detection of a
Remote Fault.
1
No interrupt.0
This bit is cleared by reading the value.
0RORFLTIS5
Link Down Interrupt
DescriptionValue
An interrupt has been generated because the LINK bit in MR1
is clear.
1
No interrupt.0
This bit is cleared by reading the value.
0ROLDIS4
811July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.