Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008
This register configures the receiver and controls the types of frames that are received.
It is important to note that when the receiver is enabled, all valid frames with a broadcast address
of FF-FF-FF-FF-FF-FF in the Destination Address field are received and stored in the RX FIFO,
even if the AMUL bit is not set.
Ethernet MAC Receive Control (MACRCTL)
Base 0x4004.8000
Offset 0x008
Type R/W, reset 0x0000.0008
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXENAMULPRMSBADCRCRSTFIFOreserved
R/WR/WR/WR/WR/WROROROROROROROROROROROType
0001000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:5
Clear Receive FIFO
DescriptionValue
Clear the receive FIFO. The receive FIFO should be cleared
when software initialization is performed.
1
No effect.0
This bit is automatically cleared when read.
The receiver should be disabled (RXEN = 0), before a reset is initiated
(RSTFIFO = 1). This sequence flushes and resets the RX FIFO.
0R/WRSTFIFO4
Enable Reject Bad CRC
DescriptionValue
Enables the rejection of frames with an incorrectly calculated
CRC. If a bad CRC is encountered, the RXERbit in the MACRIS
register is set and the receiver FIFO is reset.
1
Disables the rejection of frames with an incorrectly calculated
CRC.
0
1R/WBADCRC3
Enable Promiscuous Mode
DescriptionValue
Enables Promiscuous mode, which accepts all valid frames,
regardless of the specified Destination Address.
1
Disables Promiscuous mode, accepting only frames with the
programmed Destination Address.
0
0R/WPRMS2
July 24, 2012776
Texas Instruments-Production Data
Ethernet Controller
OBSOLETE: TI has discontinued production of this device.
