Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the
interrupt, while setting the bit enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXINTMTXERMTXEMPMFOVMRXERMMDINTMPHYINTMreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
1111111000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
Mask PHY Interrupt
DescriptionValue
An interrupt is sent to the interrupt controller when the PHYINT
bit in the MACRIS/MACIACK register is set.
1
The PHYINT interrupt is suppressed and not sent to the interrupt
controller.
0
1R/WPHYINTM6
Mask MII Transaction Complete
DescriptionValue
An interrupt is sent to the interrupt controller when the MDINT
bit in the MACRIS/MACIACK register is set.
1
The MDINT interrupt is suppressed and not sent to the interrupt
controller.
0
1R/WMDINTM5
Mask Receive Error
DescriptionValue
An interrupt is sent to the interrupt controller when the RXER bit
in the MACRIS/MACIACK register is set.
1
The RXER interrupt is suppressed and not sent to the interrupt
controller.
0
1R/WRXERM4
July 24, 2012774
Texas Instruments-Production Data
Ethernet Controller
OBSOLETE: TI has discontinued production of this device.