be enabled before the registers can be programmed (see page 263). There must be a delay of 3
system clocks after the Ethernet module clock is enabled before any Ethernet module registers are
accessed. In addition, the Ethernet oscillator is powered down when the EPHY0 bit in the Run Mode
Clock Gating Control Register 2 (RCGC2) register is clear. After setting the EPHY0 bit, software
must wait 3.5 ms before accessing any of the MII Management registers.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers and are detailed in
Section 22.2.4 of the IEEE 802.3 specification. Table 16-4 on page 769 also lists these MII
Management registers. All addresses given are absolute and are written directly to the REGADRfield
of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15
are defined by the IEEE specification and are common to all PHY layer implementations. The only
variance allowed is for features that may or may not be supported by a specific PHY implementation.
Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a
vendor's PHY implementation.
Table 16-4. Ethernet Register Map
See
page
DescriptionResetTypeNameOffset
Ethernet MAC (Ethernet Offset)
771Ethernet MAC Raw Interrupt Status/Acknowledge0x0000.0000R/W1CMACRIS/MACIACK0x000
774Ethernet MAC Interrupt Mask0x0000.007FR/WMACIM0x004
776Ethernet MAC Receive Control0x0000.0008R/WMACRCTL0x008
778Ethernet MAC Transmit Control0x0000.0000R/WMACTCTL0x00C
780Ethernet MAC Data0x0000.0000R/WMACDATA0x010
782Ethernet MAC Individual Address 00x0000.0000R/WMACIA00x014
783Ethernet MAC Individual Address 10x0000.0000R/WMACIA10x018
784Ethernet MAC Threshold0x0000.003FR/WMACTHR0x01C
786Ethernet MAC Management Control0x0000.0000R/WMACMCTL0x020
788Ethernet MAC Management Divider0x0000.0080R/WMACMDV0x024
789Ethernet MAC Management Transmit Data0x0000.0000R/WMACMTXD0x02C
790Ethernet MAC Management Receive Data0x0000.0000R/WMACMRXD0x030
791Ethernet MAC Number of Packets0x0000.0000ROMACNP0x034
792Ethernet MAC Transmission Request0x0000.0000R/WMACTR0x038
793Ethernet MAC LED Encoding0x0000.0100R/WMACLED0x040
795Ethernet PHY MDIX0x0000.0000R/WMDIX0x044
MII Management (Accessed through the MACMCTL register)
796Ethernet PHY Management Register 0 – Control0x1000R/WMR0-
798Ethernet PHY Management Register 1 – Status0x7809ROMR1-
800
Ethernet PHY Management Register 2 – PHY Identifier
1
0x0161ROMR2-
769July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
