– Halo TG110-S050
– PCA EPF8023G
– Pulse PE-68515
– Valor ST6118
– YCL 20PMT04
■ Isolation transformers with integrated RJ45 connector
– TDK TLA-6T704
– Delta RJS-1A08T089A
■ Isolation transformers with integrated RJ45 connector, LEDs and termination resistors
– Pulse J0011D21B/E
– Pulse J3011G21DNL
16.4.2 Software Configuration
To use the Ethernet Controller, it must be enabled by setting the EPHY0 and EMAC0 bits in the
RCGC2 register (see page 263). In addition, the clock to the appropriate GPIO module must be
enabled via the RCGC2 register in the System Control module. See page 263. To find out which
GPIO port to enable, refer to Table 21-4 on page 941. Configure the PMCn fields in the GPIOPCTL
register to assign the Ethernet signals to the appropriate pins. See page 447 and Table
21-5 on page 948.
The following steps can then be used to configure the Ethernet Controller for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value should be 0x03 or greater.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using
a value of 0x18.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA)
register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register
to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available
for the next transmit frame.
7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP)
register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA
register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet()
API or compare the number of bytes received to the Length field from the frame to determine
when the packet has been completely read.
16.5 Register Map
Table 16-4 on page 769 lists the Ethernet MAC and MII Management registers. The MAC register
addresses given are relative to the Ethernet base address of 0x4004.8000. The MII Management
registers are accessed using the MACMCTL register. Note that the Ethernet controller clocks must
July 24, 2012768
Texas Instruments-Production Data
Ethernet Controller
OBSOLETE: TI has discontinued production of this device.
