16.1 Block Diagram
As shown in Figure 16-1 on page 758, the Ethernet Controller is functionally divided into two layers:
the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These layers
correspond to the OSI model layers 2 and 1, respectively. The CPU accesses the Ethernet Controller
via the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames.
The MAC layer also provides the interface to the PHY layer via an internal Media Independent
Interface (MII). The PHY layer communicates with the Ethernet bus.
Figure 16-1. Ethernet Controller
ARM Cortex M3
Ethernet Controller
Media
Access
Controller
Physical
Layer Entity
MAC
(Layer 2)
PHY
(Layer 1)
RJ45
Magnetics
Figure 16-2 on page 758 shows more detail of the internal structure of the Ethernet Controller and
how the register set relates to various functions.
Figure 16-2. Ethernet Controller Block Diagram
MACRIS
MACIACK
MACIM
Interrupt
Control
MACRCTL
MACNP
Receive
Control
MACTCTL
MACTHR
MACTR
Transmit
Control
Transmit
FIFO
Receive
FIFO
MACIA0
MACIA1
Individual
Address
MACMCTL
MACMDV
MII
Control
MACDDATA
Data
Access
MDIX
Clock
Reference
Transmit
Encoding
Pulse
Shaping
Receive
Decoding
Clock
Recovery
Auto
Negotiation
Carrier
Sense
Collision
Detect
XTALNPHY
XTALPPHY
LED0
LED1
MACMTXD
MACMRXD
Interrupt
MDIX
MACLED
MAC LED
MR4
MR0
MR3
MR1
Media Independent Interface
Management Register Set
MR2
MR5
TXOP
TXON
RXIP
RXIN
MR29
MR6
MR27
MR16 MR17
MR30
MR31
July 24, 2012758
Texas Instruments-Production Data
Ethernet Controller
OBSOLETE: TI has discontinued production of this device.