Register 15: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x814
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x814
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAMIS
STARTMIS
STOPMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:3
Stop Condition Masked Interrupt Status
DescriptionValue
An unmasked STOP condition interrupt was signaled is pending.1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
0ROSTOPMIS2
Start Condition Masked Interrupt Status
DescriptionValue
An unmasked START condition interrupt was signaled is
pending.
1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
0ROSTARTMIS1
Data Masked Interrupt Status
DescriptionValue
An unmasked data received or data requested interrupt was
signaled is pending.
1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
0RODATAMIS0
755July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.