Register 13: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x80C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x80C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAIMSTARTIMSTOPIMreserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:3
Stop Condition Interrupt Mask
DescriptionValue
The STOP condition interrupt is sent to the interrupt controller
when the STOPRIS bit in the I2CSRIS register is set.
1
The STOPRIS interrupt is suppressed and not sent to the
interrupt controller.
0
0R/WSTOPIM2
Start Condition Interrupt Mask
DescriptionValue
The START condition interrupt is sent to the interrupt controller
when the STARTRIS bit in the I2CSRIS register is set.
1
The STARTRIS interrupt is suppressed and not sent to the
interrupt controller.
0
0R/WSTARTIM1
Data Interrupt Mask
DescriptionValue
The data received or data requested interrupt is sent to the
interrupt controller when the DATARIS bit in the I2CSRIS register
is set.
1
The DATARIS interrupt is suppressed and not sent to the
interrupt controller.
0
0R/WDATAIM0
753July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.