Register 11: I
2
C Slave Control/Status (I2CSCSR), offset 0x804
This register functions as a control register when written, and a status register when read.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x804
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RREQTREQFBRreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
First Byte Received
DescriptionValue
The first byte following the slave’s own address has been
received.
1
The first byte has not been received.0
This bit is only valid when the RREQ bit is set and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
0ROFBR2
Transmit Request
DescriptionValue
The I
2
C controller has been addressed as a slave transmitter
and is using clock stretching to delay the master until data has
been written to the I2CSDR register.
1
No outstanding transmit request.0
0ROTREQ1
Receive Request
DescriptionValue
The I
2
C controller has outstanding receive data from the I
2
C
master and is using clock stretching to delay the master until
the data has been read from the I2CSDR register.
1
No outstanding receive data.0
0RORREQ0
July 24, 2012750
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
OBSOLETE: TI has discontinued production of this device.
