Table 2-4. Memory Map (continued)
For details,
see page ...
DescriptionEndStart
312Flash memory control0x400F.DFFF0x400F.D000
193System control0x400F.EFFF0x400F.E000
369µDMA0x400F.FFFF0x400F.F000
-Reserved0x41FF.FFFF0x4010.0000
-Bit-banded alias of 0x4000.0000 through 0x400F.FFFF0x43FF.FFFF0x4200.0000
-
Reserved0xDFFF.FFFF0x4400.0000
Private Peripheral Bus
56Instrumentation Trace Macrocell (ITM)0xE000.0FFF0xE000.0000
56Data Watchpoint and Trace (DWT)0xE000.1FFF0xE000.1000
56Flash Patch and Breakpoint (FPB)0xE000.2FFF0xE000.2000
-Reserved0xE000.DFFF0xE000.3000
105Cortex-M3 Peripherals (SysTick, NVIC, MPU and SCB)0xE000.EFFF0xE000.E000
-Reserved0xE003.FFFF0xE000.F000
57Trace Port Interface Unit (TPIU)0xE004.0FFF0xE004.0000
-
Reserved0xFFFF.FFFF0xE004.1000
2.4.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 76).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
75July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
