Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IMreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
Interrupt Mask
DescriptionValue
The master interrupt is sent to the interrupt controller when the
RIS bit in the I2CMRIS register is set.
1
The RIS interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WIM0
July 24, 2012744
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
OBSOLETE: TI has discontinued production of this device.