Table 15-4. Inter-Integrated Circuit (I
2
C) Interface Register Map (continued)
See
page
DescriptionResetTypeNameOffset
746I2C Master Masked Interrupt Status0x0000.0000ROI2CMMIS0x018
747I2C Master Interrupt Clear0x0000.0000WOI2CMICR0x01C
748I2C Master Configuration0x0000.0000R/WI2CMCR0x020
I
2
C Slave
749I2C Slave Own Address0x0000.0000R/WI2CSOAR0x800
750I2C Slave Control/Status0x0000.0000ROI2CSCSR0x804
752I2C Slave Data0x0000.0000R/WI2CSDR0x808
753I2C Slave Interrupt Mask0x0000.0000R/WI2CSIMR0x80C
754I2C Slave Raw Interrupt Status0x0000.0000ROI2CSRIS0x810
755I2C Slave Masked Interrupt Status0x0000.0000ROI2CSMIS0x814
756I2C Slave Interrupt Clear0x0000.0000WOI2CSICR0x818
15.6 Register Descriptions (I
2
C Master)
The remainder of this section lists and describes the I
2
C master registers, in numerical order by
address offset.
735July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.