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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
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功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (20MHz/(2*(6+4)*100000))-1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
8. Specify the slave address of the master and that the next operation is a Transmit by writing the
I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
9. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the
desired data.
10. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register
with a value of 0x0000.0007 (STOP, START, RUN).
11. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
15.5 Register Map
Table 15-4 on page 734 lists the I
2
C registers. All addresses given are relative to the I
2
C base address:
I
2
C 0: 0x4002.0000
I
2
C 1: 0x4002.1000
Note that the I
2
C module clock must be enabled before the registers can be programmed (see
page 254). There must be a delay of 3 system clocks after the I
2
C module clock is enabled before
any I
2
C module registers are accessed.
The hw_i2c.h file in the StellarisWare
®
Driver Library uses a base address of 0x800 for the I
2
C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare
uses an offset between 0x000 and 0x018 with the slave base address.
Table 15-4. Inter-Integrated Circuit (I
2
C) Interface Register Map
See
page
DescriptionResetTypeNameOffset
I
2
C Master
736I2C Master Slave Address0x0000.0000R/WI2CMSA0x000
737I2C Master Control/Status0x0000.0020R/WI2CMCS0x004
742I2C Master Data0x0000.0000R/WI2CMDR0x008
743I2C Master Timer Period0x0000.0001R/WI2CMTPR0x00C
744I2C Master Interrupt Mask0x0000.0000R/WI2CMIMR0x010
745I2C Master Raw Interrupt Status0x0000.0000ROI2CMRIS0x014
July 24, 2012734
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
OBSOLETE: TI has discontinued production of this device.
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