Figure 15-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1
to I2CSCSR
Read I2CSCSR
RREQ bit=1?
Read data from
I2CSDR
YES
TREQ bit=1?
NO
Write data to
I2CSDR
YES
NO
FBR is
also valid
15.4 Initialization and Configuration
The following example shows how to configure the I
2
C module to transmit a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I
2
C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module (see page 254).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module (see page 263). To find out which GPIO port to enable, refer to Table 21-5 on page 948.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register (see page 430). To determine which GPIOs to configure, see Table
21-4 on page 941.
4. Enable the I
2
C pins for open-drain operation. See page 435.
5. Configure the PMCn fields in the GPIOPCTL register to assign the I
2
C signals to the appropriate
pins. See page 447 and Table 21-5 on page 948.
6. Initialize the I
2
C Master by writing the I2CMCR register with a value of 0x0000.0010.
733July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.