Figure 15-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
Sequence may be
omitted in a Single
Master system
BUSBSY bit=0?
NO
Write ---00111
to I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
NO
NO
Read data from
I2CMDR
YES
July 24, 2012728
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
OBSOLETE: TI has discontinued production of this device.