15.3.2.1 Standard and Fast Modes
Standard and Fast modes are selected using a value in the I
2
C Master Timer Period (I2CMTPR)
register that results in an SCL frequency of 100 kbps for Standard mode.
The I
2
C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2CMTPR register (see page 743).
The I
2
C clock period is calculated as follows:
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/SCL_PERIOD = 333 Khz
Table 15-3 gives examples of the timer periods that should be used to generate SCL frequencies
based on various system clock frequencies.
Table 15-3. Examples of I
2
C Master Timer Period versus Speed Mode
Fast ModeTimer PeriodStandard ModeTimer PeriodSystem Clock
--100 Kbps0x014 MHz
--100 Kbps0x026 MHz
312 Kbps0x0189 Kbps0x0612.5 MHz
278 Kbps0x0293 Kbps0x0816.7 MHz
333 Kbps0x02100 Kbps0x0920 MHz
312 Kbps0x0396.2 Kbps0x0C25 MHz
330 Kbps0x0497.1 Kbps0x1033 MHz
400 Kbps0x04100 Kbps0x1340 MHz
357 Kbps0x06100 Kbps0x1850 MHz
400 Kbps0x09100 Kbps0x2780 MHz
15.3.3 Interrupts
The I
2
C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master arbitration lost
July 24, 2012724
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
OBSOLETE: TI has discontinued production of this device.