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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
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功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
Table 15-2. I2C Signals (108BGA) (continued)
DescriptionBuffer Type
a
Pin TypePin Mux / Pin
Assignment
Pin NumberPin Name
I
2
C module 1 clock.ODI/OPG0 (3)
PA0 (8)
PA6 (1)
K1
L3
L6
I2C1SCL
I
2
C module 1 data.ODI/OPG1 (3)
PA1 (8)
PA7 (1)
K2
M3
M6
I2C1SDA
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.3 Functional Description
Each I
2
C module is comprised of both master and slave functions. For proper operation, the SDA
and SCL pins must be configured as open-drain signals. A typical I
2
C bus configuration is shown
in Figure 15-2.
See “Inter-Integrated Circuit (I
2
C) Interface” on page 995 for I
2
C timing diagrams.
Figure 15-2. I
2
C Bus Configuration
R
PUP
Stellaris®
I2CSCL I2CSDA
R
PUP
3rd Party Device
with I
2
C Interface
SCL SDA
I
2
C Bus
SCL
SDA
3rd Party Device
with I
2
C Interface
SCL SDA
15.3.1 I
2
C Bus Functional Overview
The I
2
C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I
2
C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 721) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
15.3.1.1 START and STOP Conditions
The protocol of the I
2
C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
15-3.
721July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
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