15.1 Block Diagram
Figure 15-1. I
2
C Block Diagram
I
2
C I/O Select
I
2
C Master Core
Interrupt
I
2
C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIMR
I2CSRIS
I2CSMIS
I2CSICRI2CMMIS
I
2
C Control
15.2 Signal Description
The following table lists the external signals of the I
2
C interface and describes the function of each.
The I
2
C interface signals are alternate functions for some GPIO signals and default to be GPIO
signals at reset., with the exception of the I2C0SCL and I2CSDA pins which default to the I
2
C
function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for the I
2
C signals. The AFSELbit in the GPIO Alternate Function Select (GPIOAFSEL)
register (page 430) should be set to choose the I
2
C function. The number in parentheses is the
encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL)
register (page 447) to assign the I
2
C signal to the specified GPIO port pin. Note that the I
2
C pins
should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 408.
Table 15-1. I2C Signals (100LQFP)
DescriptionBuffer Type
a
Pin TypePin Mux / Pin
Assignment
Pin NumberPin Name
I
2
C module 0 clock.ODI/OPB2 (1)70I2C0SCL
I
2
C module 0 data.ODI/OPB3 (1)71I2C0SDA
I
2
C module 1 clock.ODI/OPG0 (3)
PA0 (8)
PA6 (1)
19
26
34
I2C1SCL
I
2
C module 1 data.ODI/OPG1 (3)
PA1 (8)
PA7 (1)
18
27
35
I2C1SDA
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 15-2. I2C Signals (108BGA)
DescriptionBuffer Type
a
Pin TypePin Mux / Pin
Assignment
Pin NumberPin Name
I
2
C module 0 clock.ODI/OPB2 (1)C11I2C0SCL
I
2
C module 0 data.ODI/OPB3 (1)C12I2C0SDA
July 24, 2012720
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
OBSOLETE: TI has discontinued production of this device.