Register 10: SSI DMA Control (SSIDMACTL), offset 0x024
The SSIDMACTL register is the µDMA control register.
SSI DMA Control (SSIDMACTL)
SSI0 base: 0x4000.8000
Offset 0x024
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXDMAETXDMAEreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:2
Transmit DMA Enable
DescriptionValue
µDMA for the transmit FIFO is disabled.0
µDMA for the transmit FIFO is enabled.1
0R/WTXDMAE1
Receive DMA Enable
DescriptionValue
µDMA for the receive FIFO is disabled.0
µDMA for the receive FIFO is enabled.1
0R/WRXDMAE0
July 24, 2012706
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
OBSOLETE: TI has discontinued production of this device.