DescriptionResetTypeNameBit/Field
SSI Receive Overrun Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the receive FIFO
overflowing.
1
This bit is cleared when a 1 is written to the RORIC bit in the SSI
Interrupt Clear (SSIICR) register.
0RORORMIS0
July 24, 2012704
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
OBSOLETE: TI has discontinued production of this device.