Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORMISRTMISRXMISTXMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:4
SSI Transmit FIFO Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the transmit FIFO
being half empty or less (if the EOT bit is clear) or due to the
transmission of the last data bit (if the EOT bit is set).
1
This bit is cleared when the transmit FIFO is more than half empty (if
the EOT bit is clear) or when it has any data in it (if the EOT bit is set).
0ROTXMIS3
SSI Receive FIFO Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the receive FIFO
being half full or more.
1
This bit is cleared when the receive FIFO is less than half full.
0RORXMIS2
SSI Receive Time-Out Masked Interrupt Status
DescriptionValue
An interrupt has not occurred or is masked.0
An unmasked interrupt was signaled due to the receive time
out.
1
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
0RORTMIS1
703July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.