Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
Offset 0x018
Type RO, reset 0x0000.0008
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORRISRTRISRXRISTXRISreserved
ROROROROROROROROROROROROROROROROType
0001000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:4
SSI Transmit FIFO Raw Interrupt Status
DescriptionValue
No interrupt.0
If the EOT bit in the SSICR1 register is clear, the transmit FIFO
is half empty or less.
If the EOT bit is set, the transmit FIFO is empty, and the last bit
has been transmitted out of the serializer.
1
This bit is cleared when the transmit FIFO is more than half full (if the
EOT bit is clear) or when it has any data in it (if the EOT bit is set).
1ROTXRIS3
SSI Receive FIFO Raw Interrupt Status
DescriptionValue
No interrupt.0
The receive FIFO is half full or more.1
This bit is cleared when the receive FIFO is less than half full.
0RORXRIS2
SSI Receive Time-Out Raw Interrupt Status
DescriptionValue
No interrupt.0
The receive time-out has occurred.1
This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt
Clear (SSIICR) register.
0RORTRIS1
701July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.