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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
  • LM3S6G65-IQC80-A2T PDF在线浏览
功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
Register 3: SSI Data (SSIDR), offset 0x008
Important: This register is read-sensitive. See the register description for details.
The SSIDR register is 16-bits wide. When the SSIDR register is read, the entry in the receive FIFO
that is pointed to by the current FIFO read pointer is accessed. When a data value is removed by
the SSI receive logic from the incoming data frame, it is placed into the entry in the receive FIFO
pointed to by the current FIFO write pointer.
When the SSIDR register is written to, the entry in the transmit FIFO that is pointed to by the write
pointer is written to. Data values are removed from the transmit FIFO one value at a time by the
transmit logic. Each data value is loaded into the transmit serial shifter, then serially shifted out onto
the SSITx pin at the programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is cleared, allowing the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
0x0000R/WDATA15:0
July 24, 2012696
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
OBSOLETE: TI has discontinued production of this device.
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