Register 2: SSI Control 1 (SSICR1), offset 0x004
The SSICR1 register contains bit fields that control various functions within the SSI module. Master
and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
LBMSSEMSSODEOTreserved
R/WR/WR/WR/WR/WROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:5
End of Transmission
DescriptionValue
The TXRIS interrupt indicates that the transmit FIFO is half full
or less.
0
The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.
1
0R/WEOT4
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
DescriptionValue
SSI can drive the SSITx output in Slave mode.0
SSI must not drive the SSITx output in Slave mode.1
0R/WSOD3
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
the SSI is disabled (SSE=0).
DescriptionValue
The SSI is configured as a master.0
The SSI is configured as a slave.1
0R/WMS2
July 24, 2012694
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
OBSOLETE: TI has discontinued production of this device.
