Register 15: UART LIN Control (UARTLCTL), offset 0x090
The UARTLCTL register is the configures the operation of the UART when in LIN mode.
UART LIN Control (UARTLCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x090
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MASTERreservedBLENreserved
R/WROROROR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:6
Sync Break Length
DescriptionValue
Sync break length is 16T bits0x3
Sync break length is 15T bits0x2
Sync break length is 14T bits0x1
Sync break length is 13T bits (default)0x0
0x0R/WBLEN5:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:1
LIN Master Enable
DescriptionValue
The UART operates as a LIN master.1
The UART operates as a LIN slave.0
0R/WMASTER0
July 24, 2012662
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
OBSOLETE: TI has discontinued production of this device.