Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RIMICCTSMICDCDMICDSRMICRXICTXICRTICFEICPEICBEICOEICreservedLMSBICLME1ICLME5IC
W1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CROROW1CW1CW1CType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:16
LIN Mode Edge 5 Interrupt Clear
Writing a 1 to this bit clears the LME5RIS bit in the UARTRIS register
and the LME5MIS bit in the UARTMIS register.
0W1CLME5IC15
LIN Mode Edge 1 Interrupt Clear
Writing a 1 to this bit clears the LME1RIS bit in the UARTRIS register
and the LME1MIS bit in the UARTMIS register.
0W1CLME1IC14
LIN Mode Sync Break Interrupt Clear
Writing a 1 to this bit clears the LMSBRIS bit in the UARTRIS register
and the LMSBMIS bit in the UARTMIS register.
0W1CLMSBIC13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved12:11
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and
the OEMIS bit in the UARTMIS register.
0W1COEIC10
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and
the BEMIS bit in the UARTMIS register.
0W1CBEIC9
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and
the PEMIS bit in the UARTMIS register.
0W1CPEIC8
659July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.