DescriptionResetTypeNameBit/Field
UART Transmit Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to passing through
the specified transmit FIFO level (if the EOT bit is clear) or due
to the transmission of the last data bit (if the EOT bit is set).
1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
0ROTXMIS5
UART Receive Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
0RORXMIS4
UART Data Set Ready Modem Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to Data Set Ready.1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0RODSRMIS3
UART Data Carrier Detect Modem Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to Data Carrier Detect.1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0RODCDMIS2
657July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.