Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RIMISCTSMISDCDMISDSRMISRXMISTXMISRTMISFEMISPEMISBEMISOEMISreservedLMSBMISLME1MISLME5MIS
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:16
LIN Mode Edge 5 Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to the 5th falling edge
of the LIN Sync Field.
1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR
register.
0ROLME5MIS15
LIN Mode Edge 1 Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to the 1st falling edge
of the LIN Sync Field.
1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR
register.
0ROLME1MIS14
LIN Mode Sync Break Masked Interrupt Status
DescriptionValue
An unmasked interrupt was signaled due to the receipt of a LIN
Sync Break.
1
An interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR
register.
0ROLMSBMIS13
655July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.