DescriptionResetTypeNameBit/Field
UART Transmit Raw Interrupt Status
DescriptionValue
If the EOT bit in the UARTCTL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
If the EOT bit is set, the last bit of all transmitted data and flags
has left the serializer.
1
No interrupt0
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
0ROTXRIS5
UART Receive Raw Interrupt Status
DescriptionValue
The receive FIFO level has passed through the condition defined
in the UARTIFLS register.
1
No interrupt0
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
0RORXRIS4
UART Data Set Ready Modem Raw Interrupt Status
DescriptionValue
Data Set Ready used for software flow control.1
No interrupt0
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0RODSRRIS3
UART Data Carrier Detect Modem Raw Interrupt Status
DescriptionValue
Data Carrier Detect used for software flow control.1
No interrupt0
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0RODCDRIS2
653July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.