Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
Note that bits [3:0] are only implemented on UART1. These bits are reserved on UART0 and UART2.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x038
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RIIMCTSIMDCDIMDSRIMRXIMTXIMRTIMFEIMPEIMBEIMOEIMreservedLMSBIMLME1IMLME5IM
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:16
LIN Mode Edge 5 Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the LME5RIS
bit in the UARTRIS register is set.
1
The LME5RIS interrupt is suppressed and not sent to the
interrupt controller.
0
0R/WLME5IM15
LIN Mode Edge 1 Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the LME1RIS
bit in the UARTRIS register is set.
1
The LME1RIS interrupt is suppressed and not sent to the
interrupt controller.
0
0R/WLME1IM14
LIN Mode Sync Break Interrupt Mask
DescriptionValue
An interrupt is sent to the interrupt controller when the LMSBRIS
bit in the UARTRIS register is set.
1
The LMSBRIS interrupt is suppressed and not sent to the
interrupt controller.
0
0R/WLMSBIM13
647July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.