DescriptionResetTypeNameBit/Field
Enable Clear To Send
DescriptionValue
CTS hardware flow control is enabled. Data is only transmitted
when the U1CTS signal is asserted.
1
CTS hardware flow control is disabled.0
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0R/WCTSEN15
Enable Request to Send
DescriptionValue
RTS hardware flow control is enabled. Data is only requested
(by asserting U1RTS) when the receive FIFO has available
entries.
1
RTS hardware flow control is disabled.0
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0R/WRTSEN14
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved13:12
Request to Send
When RTSEN is clear, the status of this bit is reflected on the U1RTS
signal. If RTSENis set, this bit is ignored on a write and should be ignored
on read.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0R/WRTS11
Data Terminal Ready
This bit sets the state of the U1DTR output.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0R/WDTR10
UART Receive Enable
DescriptionValue
The receive section of the UART is enabled.1
The receive section of the UART is disabled.0
If the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
1R/WRXE9
July 24, 2012642
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
OBSOLETE: TI has discontinued production of this device.