Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register stores the 8-bit low-power counter divisor value used to derive the low-power
SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared when
reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / F
IrLPBaud16
where F
IrLPBaud16
is nominally 1.8432 MHz.
The divisor must be programmed such that 1.42 MHz < F
IrLPBaud16
< 2.12 MHz, resulting in a
low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum
frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected,
but pulses greater than 1.4 μs are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x020
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ILPDVSRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
IrDA Low-Power Divisor
This field contains the 8-bit low-power divisor value.
0x00R/WILPDVSR7:0
July 24, 2012636
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
OBSOLETE: TI has discontinued production of this device.