DescriptionResetTypeNameBit/Field
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
DescriptionValue
If the FIFO is disabled (FEN is 0), the receive holding register
is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.
1
The receiver can receive data.0
0RORXFF6
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
DescriptionValue
If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
1
The transmitter is not full.0
0ROTXFF5
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
DescriptionValue
If the FIFO is disabled (FEN is 0), the receive holding register
is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
1
The receiver is not empty.0
1RORXFE4
UART Busy
DescriptionValue
The UART is busy transmitting data. This bit remains set until
the complete byte, including all stop bits, has been sent from
the shift register.
1
The UART is not busy.0
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
0ROBUSY3
Data Carrier Detect
DescriptionValue
The U1DCD signal is asserted.1
The U1DCD signal is not asserted.0
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0RODCD2
July 24, 2012634
Texas Instruments-Production Data
Universal Asynchronous Receivers/Transmitters (UARTs)
OBSOLETE: TI has discontinued production of this device.
