Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1. The RI, DCD, DSR and CTS bits indicate the modem flow control and
status. Note that the modem bits are only implemented on UART1 and are reserved on UART0 and
UART2.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x018
Type RO, reset 0x0000.0090
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CTSDSRDCDBUSYRXFETXFFRXFFTXFERIreserved
ROROROROROROROROROROROROROROROROType
0000100100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:9
Ring Indicator
DescriptionValue
The U1RI signal is asserted.1
The U1RI signal is not asserted.0
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
0RORI8
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
DescriptionValue
If the FIFO is disabled (FEN is 0), the transmit holding register
is empty.
If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
1
The transmitter has data to transmit.0
1ROTXFE7
633July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
