Table 13-2. UART Signals (108BGA) (continued)
DescriptionBuffer Type
a
Pin TypePin Mux / Pin
Assignment
Pin NumberPin Name
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
TTLIPD0 (4)
PG0 (1)
PB4 (4)
PD5 (9)
G1
K1
A6
B4
U2Rx
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTLOPE4 (5)
PD1 (4)
PG1 (1)
PD6 (9)
B2
G2
K2
A3
U2Tx
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3 Functional Description
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 641). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to
an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
13.3.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits
(LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 13-2 on page 617 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 13-2. UART Character Frame
1
0
5-8 data bits
LSB
MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
13.3.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divisor allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 637) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
617July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
