– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
13.1 Block Diagram
Figure 13-1. UART Module Block Diagram
TxFIFO
16 x 8
.
.
.
RxFIFO
16 x 8
.
.
.
DMA Control
UARTDMACTL
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
Interrupt Control
UARTDR
Control/Status
Transmitter
(with SIR
Transmit
Encoder)
Baud Rate
Generator
Receiver
(with SIR
Receive
Decoder)
UnTx
UnRx
DMA Request
System Clock
Interrupt
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
UARTIBRD
UARTFBRD
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
UARTLCTL
UARTLSS
UARTLTIM
13.2 Signal Description
The following table lists the external signals of the UART module and describes the function of each.
The UART signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset, with the exception of the U0Rxand U0Tx pins which default to the UART function. The column
in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these
UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register
(page 430) should be set to choose the UART function. The number in parentheses is the encoding
that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register
(page 447) to assign the UART signal to the specified GPIO port pin. For more information on
configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 408.
615July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
