Register 35: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for a sample executed with Sample Sequencer
3. The END0 bit is always set as this sequencer can execute only one sample. This register is 4 bits
wide and contains information for one possible sample. See the ADCSSCTL0 register on page 584
for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A4
Type R/W, reset 0x0000.0002
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
D0END0IE0TS0reserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
1st Sample Temp Sensor Select
Same definition as TS7 but used during the first sample.
0R/WTS03
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
0R/WIE02
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Because this sequencer has only one entry, this bit must be set.
1R/WEND01
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0R/WD00
601July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.