Table 2-2. Processor Register Map
See
page
DescriptionResetTypeNameOffset
61Cortex General-Purpose Register 0-R/WR0-
61Cortex General-Purpose Register 1-R/WR1-
61Cortex General-Purpose Register 2-R/WR2-
61Cortex General-Purpose Register 3-R/WR3-
61Cortex General-Purpose Register 4-R/WR4-
61Cortex General-Purpose Register 5-R/WR5-
61Cortex General-Purpose Register 6-R/WR6-
61Cortex General-Purpose Register 7-R/WR7-
61Cortex General-Purpose Register 8-R/WR8-
61Cortex General-Purpose Register 9-R/WR9-
61Cortex General-Purpose Register 10-R/WR10-
61Cortex General-Purpose Register 11-R/WR11-
61Cortex General-Purpose Register 12-R/WR12-
62Stack Pointer-R/WSP-
63Link Register0xFFFF.FFFFR/WLR-
64Program Counter-R/WPC-
65Program Status Register0x0100.0000R/WPSR-
69Priority Mask Register0x0000.0000R/WPRIMASK-
70Fault Mask Register0x0000.0000R/WFAULTMASK-
71Base Priority Mask Register0x0000.0000R/WBASEPRI-
72Control Register0x0000.0000R/WCONTROL-
2.3.4 Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 59.
The core registers are not memory mapped and are accessed by register name rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
July 24, 201260
Texas Instruments-Production Data
The Cortex-M3 Processor
OBSOLETE: TI has discontinued production of this device.