the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 62).
In Thread mode, the CONTROL register (see page 72) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 59.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Stack UsedPrivilege LevelUseProcessor Mode
Main stack or process stack
a
Privileged or unprivileged
a
ApplicationsThread
Main stackAlways privilegedException handlersHandler
a. See CONTROL (page 72).
2.3.3 Register Map
Figure 2-3 on page 59 shows the Cortex-M3 register set. Table 2-2 on page 60 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
Figure 2-3. Cortex-M3 Register Set
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP
‡
PSP
‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡
Banked version of SP
59July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
