6. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority and Sample
Sequencer 3 as the lowest priority.
12.4.2 Sample Sequencer Configuration
Configuration of the sample sequencers is slightly more complex than the module initialization
because each sample sequencer is completely programmable.
The configuration for each sample sequencer should be as follows:
1. Ensure that the sample sequencer is disabled by clearing the corresponding ASENn bit in the
ADCACTSS register. Programming of the sample sequencers is allowed without having them
enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger
event were to occur during the configuration process.
2. Configure the trigger event for the sample sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, set the corresponding MASK bit in the ADCIM register.
6. Enable the sample sequencer logic by setting the corresponding ASENn bit in the ADCACTSS
register.
12.5 Register Map
Table 12-5 on page 553 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that ADC module's base address of:
■ ADC0: 0x4003.8000
■ ADC1: 0x4003.9000
Note that the ADC module clock must be enabled before the registers can be programmed (see
page 246). There must be a delay of 3 system clocks after the ADC module clock is enabled before
any ADC module registers are accessed.
Table 12-5. ADC Register Map
See
page
DescriptionResetTypeNameOffset
556ADC Active Sample Sequencer0x0000.0000R/WADCACTSS0x000
557ADC Raw Interrupt Status0x0000.0000ROADCRIS0x004
559ADC Interrupt Mask0x0000.0000R/WADCIM0x008
561ADC Interrupt Status and Clear0x0000.0000R/W1CADCISC0x00C
564ADC Overflow Status0x0000.0000R/W1CADCOSTAT0x010
566ADC Event Multiplexer Select0x0000.0000R/WADCEMUX0x014
553July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
