6 Hibernation Module .............................................................................................. 276
6.1 Block Diagram ............................................................................................................ 277
6.2 Signal Description ....................................................................................................... 277
6.3 Functional Description ................................................................................................. 278
6.3.1 Register Access Timing ............................................................................................... 278
6.3.2 Hibernation Clock Source ............................................................................................ 279
6.3.3 System Implementation ............................................................................................... 280
6.3.4 Battery Management ................................................................................................... 281
6.3.5 Real-Time Clock .......................................................................................................... 281
6.3.6 Battery-Backed Memory .............................................................................................. 282
6.3.7 Power Control Using HIB ............................................................................................. 282
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 282
6.3.9 Initiating Hibernate ...................................................................................................... 282
6.3.10 Waking from Hibernate ................................................................................................ 282
6.3.11 Interrupts and Status ................................................................................................... 283
6.4 Initialization and Configuration ..................................................................................... 283
6.4.1 Initialization ................................................................................................................. 283
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 284
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 284
6.4.4 External Wake-Up from Hibernation .............................................................................. 285
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 285
6.5 Register Map .............................................................................................................. 285
6.6 Register Descriptions .................................................................................................. 286
7 Internal Memory ................................................................................................... 303
7.1 Block Diagram ............................................................................................................ 303
7.2 Functional Description ................................................................................................. 303
7.2.1 SRAM ........................................................................................................................ 304
7.2.2 ROM .......................................................................................................................... 304
7.2.3 Flash Memory ............................................................................................................. 306
7.3 Register Map .............................................................................................................. 311
7.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 312
7.5 Memory Register Descriptions (System Control Offset) .................................................. 324
8 Micro Direct Memory Access (μDMA) ................................................................ 348
8.1 Block Diagram ............................................................................................................ 349
8.2 Functional Description ................................................................................................. 349
8.2.1 Channel Assignments .................................................................................................. 350
8.2.2 Priority ........................................................................................................................ 351
8.2.3 Arbitration Size ............................................................................................................ 351
8.2.4 Request Types ............................................................................................................ 351
8.2.5 Channel Configuration ................................................................................................. 352
8.2.6 Transfer Modes ........................................................................................................... 354
8.2.7 Transfer Size and Increment ........................................................................................ 362
8.2.8 Peripheral Interface ..................................................................................................... 362
8.2.9 Software Request ........................................................................................................ 362
8.2.10 Interrupts and Errors .................................................................................................... 363
8.3 Initialization and Configuration ..................................................................................... 363
8.3.1 Module Initialization ..................................................................................................... 363
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 364
5July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.