Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer 0 base: 0x4003.0000
Timer 1 base: 0x4003.1000
Timer 2 base: 0x4003.2000
Timer 3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOMISCAMMISCAEMISRTCMISTAMMISreservedTBTOMISCBMMISCBEMISTBMMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
GPTM Timer B Match Masked Interrupt
DescriptionValue
An unmasked Timer B Mode Match interrupt
has occurred.
1
A Timer B Mode Match interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
0ROTBMMIS11
GPTM Timer B Capture Mode Event Masked Interrupt
DescriptionValue
An unmasked Capture B event interrupt
has occurred.
1
A Capture B event interrupt has not occurred or is masked.0
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
0ROCBEMIS10
491July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.