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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
  • LM3S6G65-IQC80-A2T PDF在线浏览
功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
DescriptionResetTypeNameBit/Field
GPTM Timer B Capture Mode Match Raw Interrupt
DescriptionValue
The capture mode match has occurred for Timer B. This interrupt
asserts when the values in the GPTMTBR and GPTMTBPR
match the values in the GPTMTBMATCHR and GPTMTBPMR
when configured in Input Edge-Time mode.
1
The capture mode match for Timer B has not occurred.0
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR
register.
0ROCBMRIS9
GPTM Timer B Time-Out Raw Interrupt
DescriptionValue
Timer B has timed out. This interrupt is asserted when a
one-shot or periodic mode timer reaches it's count limit (0 or
the value loaded into GPTMTBILR, depending on the count
direction).
1
Timer B has not timed out.0
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR
register.
0ROTBTORIS8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:5
GPTM Timer A Match Raw Interrupt
DescriptionValue
The TAMIE bit is set in the GPTMTAMR register, and the match
value in the GPTMTAMATCHR and (optionally) GPTMTAPMR
registers have been reached when configured in one-shot or
periodic mode.
1
The match value has not been reached.0
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR
register.
0ROTAMRIS4
GPTM RTC Raw Interrupt
DescriptionValue
The RTC event has occurred.1
The RTC event has not occurred.0
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR
register.
0RORTCRIS3
489July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
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