Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer 0 base: 0x4003.0000
Timer 1 base: 0x4003.1000
Timer 2 base: 0x4003.2000
Timer 3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATORISCAMRISCAERISRTCRISTAMRISreservedTBTORISCBMRISCBERISTBMRISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
GPTM Timer B Match Raw Interrupt
DescriptionValue
The TBMIE bit is set in the GPTMTBMR register, and the match
values in the GPTMTBMATCHR and (optionally) GPTMTBPMR
registers have been reached when configured in one-shot or
periodic mode.
1
The match value has not been reached.0
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
0ROTBMRIS11
GPTM Timer B Capture Mode Event Raw Interrupt
DescriptionValue
A capture mode event has occurred for Timer B. This interrupt
asserts when the subtimer is configured in Input Edge-Time
mode.
1
The capture mode event for Timer B has not occurred.0
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
0ROCBERIS10
July 24, 2012488
Texas Instruments-Production Data
General-Purpose Timers
OBSOLETE: TI has discontinued production of this device.