Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables
the corresponding interrupt, while clearing a bit disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer 0 base: 0x4003.0000
Timer 1 base: 0x4003.1000
Timer 2 base: 0x4003.2000
Timer 3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOIMCAMIMCAEIMRTCIMTAMIMreservedTBTOIMCBMIMCBEIMTBMIMreserved
R/WR/WR/WR/WR/WROROROR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0ROreserved31:12
GPTM Timer B Match Interrupt Mask
The TBMIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WTBMIM11
GPTM Timer B Capture Mode Event Interrupt Mask
The CBEIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCBEIM10
GPTM Timer B Capture Mode Match Interrupt Mask
The CBMIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCBMIM9
July 24, 2012486
Texas Instruments-Production Data
General-Purpose Timers
OBSOLETE: TI has discontinued production of this device.