7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
10.5 Register Map
Table 10-11 on page 476 lists the GPTM registers. The offset listed is a hexadecimal increment to
the register’s address, relative to that timer’s base address:
■ Timer 0: 0x4003.0000
■ Timer 1: 0x4003.1000
■ Timer 2: 0x4003.2000
■ Timer 3: 0x4003.3000
Note that the GP Timer module clock must be enabled before the registers can be programmed
(see page 254). There must be a delay of 3 system clocks after the Timer module clock is enabled
before any Timer module registers are accessed.
Table 10-11. Timers Register Map
See
page
DescriptionResetTypeNameOffset
478GPTM Configuration0x0000.0000R/WGPTMCFG0x000
479GPTM Timer A Mode0x0000.0000R/WGPTMTAMR0x004
481GPTM Timer B Mode0x0000.0000R/WGPTMTBMR0x008
483GPTM Control0x0000.0000R/WGPTMCTL0x00C
486GPTM Interrupt Mask0x0000.0000R/WGPTMIMR0x018
488GPTM Raw Interrupt Status0x0000.0000ROGPTMRIS0x01C
491GPTM Masked Interrupt Status0x0000.0000ROGPTMMIS0x020
494GPTM Interrupt Clear0x0000.0000W1CGPTMICR0x024
496GPTM Timer A Interval Load0xFFFF.FFFFR/WGPTMTAILR0x028
497GPTM Timer B Interval Load0x0000.FFFFR/WGPTMTBILR0x02C
498GPTM Timer A Match0xFFFF.FFFFR/WGPTMTAMATCHR0x030
499GPTM Timer B Match0x0000.FFFFR/WGPTMTBMATCHR0x034
500GPTM Timer A Prescale0x0000.0000R/WGPTMTAPR0x038
501GPTM Timer B Prescale0x0000.0000R/WGPTMTBPR0x03C
502GPTM TimerA Prescale Match0x0000.0000R/WGPTMTAPMR0x040
503GPTM TimerB Prescale Match0x0000.0000R/WGPTMTBPMR0x044
504GPTM Timer A0xFFFF.FFFFROGPTMTAR0x048
505GPTM Timer B0x0000.FFFFROGPTMTBR0x04C
506GPTM Timer A Value0xFFFF.FFFFRWGPTMTAV0x050
July 24, 2012476
Texas Instruments-Production Data
General-Purpose Timers
OBSOLETE: TI has discontinued production of this device.
