by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode match interrupt is
enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnMMIS bit in
the GPTM Masked Interrupt Status (GPTMMIS) register. In this mode, the GPTMTnR register
holds the count of the input events while the GPTMTnV register holds the free-running timer value.
In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC
trigger is enabled by setting the TnOTEbit in GPTMCTL.The μDMA trigger is enabled by configuring
and enabling the appropriate μDMA channel. See “Channel Configuration” on page 352.
After the match value is reached, the counter is then reloaded using the value in GPTMTnILR and
GPTMTnPR registers, and stopped because the GPTM automatically clears the TnEN bit in the
GPTMCTL register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software.
Figure 10-3 on page 469 shows how Input Edge-Count mode works. In this case, the timer start
value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so
that four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted because the timer automatically clears the TnEN bit
after the current count matches the value in the GPTMTnMATCHR register.
Figure 10-3. Input Edge-Count Mode Example
Input Signal
Timer stops,
flags
asserted
Timer reload
on next cycle
Ignored Ignored
Count
0x000A
0x0006
0x0007
0x0008
0x0009
10.3.2.4 Input Edge-Time Mode
Note: For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
The prescaler is not available in 16-Bit Input Edge-Time mode.
In Edge-Time mode, the timer is configured as a 16-bit down-counter. In this mode, the timer is
initialized to the value loaded in the GPTMTnILRregister. The timer is capable of capturing three
types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time mode by
setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is
469July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
