and two load/initialization registers and their associated control functions. The exact functionality of
each GPTM is controlled by software and configured through the register interface. Timer A and
Timer B can be used individually, in which case they have a 16-bit counting range. In addition, Timer
A and Timer B can be concatenated to provide a 32-bit counting range. Note that the prescaler can
only be used when the timers are used individually.
The available modes for each GPTM block are shown in Table 10-4 on page 465. Note that when
counting down in one-shot or periodic modes, the prescaler acts as a true prescaler and contains
the least-significant bits of the count. When counting up in one-shot or periodic modes, the prescaler
acts as a timer extension and holds the most-significant bits of the count. In input edge count mode,
the prescaler always acts as a timer extension, regardless of the count direction.
Table 10-4. General-Purpose Timer Capabilities
Prescaler Size
a
Counter SizeCount DirectionTimer UseMode
8-bit16-bitUp or DownIndividual
One-shot
-32-bitUp or DownConcatenated
8-bit16-bitUp or DownIndividual
Periodic
-32-bitUp or DownConcatenated
-32-bitUpConcatenatedRTC
8-bit16-bitDownIndividualEdge Count
-16-bitDownIndividualEdge Time
-16-bitDownIndividualPWM
a. The prescaler is only available when the timers are used individually
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 478),
the GPTM Timer A Mode (GPTMTAMR) register (see page 479), and the GPTM Timer B Mode
(GPTMTBMR) register (see page 481). When in one of the concatentated modes, Timer A and Timer
B can only operate in one mode. However, when configured in an individual mode, Timer A and
Timer B can be independently configured in any combination of the individual modes.
10.3.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all
1s, along with their corresponding load registers: the GPTM Timer A Interval Load (GPTMTAILR)
register (see page 496) and the GPTM Timer B Interval Load (GPTMTBILR) register (see page 497)
and shadow registers: the GPTM Timer A Value (GPTMTAV) register (see page 506) and the GPTM
Timer B Value (GPTMTBV) register (see page 507). The prescale counters are initialized to 0x00:
the GPTM Timer A Prescale (GPTMTAPR) register (see page 500) and the GPTM Timer B Prescale
(GPTMTBPR) register (see page 501).
10.3.2 Timer Modes
This section describes the operation of the various timer modes. When using Timer A and Timer B
in concatenated mode, only the Timer A control and status bits must be used; there is no need to
use Timer B control and status bits. The GPTM is placed into individual/split mode by writing a value
of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 478). In the following sections,
the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer
B function. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count
mode is the value in the GPTM Timer n Interval Load (GPTMTnILR) and the optional GPTM Timer
n Prescale (GPTMTnPR) registers.
465July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
