10.1 Block Diagram
In the block diagram, the specific Capture Compare PWM (CCP) pins available depend on the
Stellaris device. See Table 10-1 on page 462 for the available CCP pins and their timer assignments.
Figure 10-1. GPTM Module Block Diagram
Clock / Edge
Detect
RTC Divider
Clock / Edge
Detect
32 KHz or
Even CCP Pin
Odd CCP Pin
TA Comparator
TB Comparator
GPTMTBR
GPTMTAR
Timer A
Interrupt
Timer B
Interrupt
System
Clock
0x0000 (Down Counter Modes)
0xFFFF (Up Counter Modes)
0x0000 (Down Counter Modes)
0xFFFF (Up Counter Modes)
En
En
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
GPTMTAV
GPTMTBV
Timer A
Free-Running
Value
Timer B
Free-Running
Value
Timer A Control
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
Timer B Control
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Table 10-1. Available CCP Pins
Odd CCP PinEven CCP Pin16-Bit Up/Down CounterTimer
-CCP0TimerATimer 0
CCP1-TimerB
-CCP2TimerATimer 1
CCP3-TimerB
-CCP4TimerATimer 2
CCP5-TimerB
-CCP6TimerATimer 3
CCP7-TimerB
10.2 Signal Description
The following table lists the external signals of the GP Timer module and describes the function of
each. The GP Timer signals are alternate functions for some GPIO signals and default to be GPIO
signals at reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible
GPIO pin placements for these GP Timer signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 430) should be set to choose the GP Timer function. The number
in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port
July 24, 2012462
Texas Instruments-Production Data
General-Purpose Timers
OBSOLETE: TI has discontinued production of this device.
