Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on
the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 438). Write access
to this register is protected with the GPIOCR register. Bits in GPIOCR that are cleared prevent writes
to the equivalent bit in this register.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-9. GPIO Pins With Non-Zero Reset Values
GPIOPCTLGPIOPURGPIOPDRGPIODENGPIOAFSELDefault StateGPIO Pins
0x10000UART0PA[1:0]
0x20000SSI0PA[5:2]
0x30000I
2
C0PB[3:2]
0x11011JTAG/SWDPC[3:0]
Note: The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7)
and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate
Function Select (GPIOAFSEL) register (see page 430), GPIO Pull Up Select (GPIOPUR)
register (see page 436), GPIO Pull-Down Select (GPIOPDR) register (see page 438), and
GPIO Digital Enable (GPIODEN) register (see page 441) are not committed to storage
unless the GPIO Lock (GPIOLOCK) register (see page 443) has been unlocked and the
appropriate bits of the GPIO Commit (GPIOCR) register (see page 444) have been set.
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
Offset 0x510
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PUEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
--------00000000Reset
July 24, 2012436
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)
OBSOLETE: TI has discontinued production of this device.